In semiconductor devices including p-n junctions, including for example simple diodes as well as more complex devices such as field effect transistors, bipolar transistors or thyristors, high doping levels reduce the series resistance. However, on the other hand, low doping levels allow high reverse voltages to be applied. There is a trade-off between these quantities, and the maximum achievable trade off for a simple diode is known as the 1D silicon limit.
A number of structures are known that can deliver better results than the 1D limit. Such structures are typically known as reduced surface field (RESURF) structures. Junction shaping, or field shaping, using field plates or semi-insulating films can be used.
An alternative approach bridges the junction using dielectric layers—EP 519 741 A2 is an example of this technique. However, these approaches all significantly add to the complexity of the manufacturing process and in particular they are not generally compatible with standard processes since they require additional mask and processing steps not present in the standard processes. There is a significant cost in adding such additional process steps.
A method for manufacturing such a RESURF device in a simplified manner has been disclosed in PCT patent publication WO2006/136979, which discloses a method of manufacturing a semiconductor device according to the opening paragraph. It has been found that although this method allows for a semiconductor device to be manufactured using standard processes, some embodiments of the semiconductor device disclosed in this publication can suffer from a limited gate dielectric lifetime depending on the manufacturing quality and process control, which manifests itself by a time-dependent dielectric breakdown (TDDB) of the gate oxide layer. The reduced robustness to process variations may also restrict product transfer and sourcing to different CMOS foundries.